Split gate non-volatile flash memory cells are known in the art, including those which have a select gate, a floating gate, a control gate, and an erase gate. For example, U.S. Pat. No. 7,927,994, which is incorporated by reference for all purposes, discloses the formation of such memory cells.
FIG. 3L of the '994 patent shows that source region 16 is formed in the substrate between two floating gates, and underneath the erase gate 24. The '994 patent describes and shows (in FIG. 3G) that source region 16 is formed by ion implantation between a pair of gates stacks, with each gate stack including a floating gate, a control gate, insulation layers, and side spacers (including the same side spacers that were used to define the inner sidewalls of the floating gates). The source region implant into the substrate is limited and defined by the inner edges of the opposing floating gates (and the side spacers over the floating gates that were used to define those edges through a polysilicon etch).
FIG. 1 is a top view of the memory array formed using the techniques of the '994 patent. The STI isolation regions 10 are disposed between columns of active regions 12 containing the memory cells. The control gate lines 14 extend parallel to the source lines 16. Spacing 18 between the control gate lines 14 and source lines 16 (i.e. the CG-to-SL spacing 18) must be sufficiently wide to avoid shorting of adjacent floating gates. Spacing 18 depends on alignment between control gate 14 and source line 16. If control gate 14 is miss-aligned to source line 16 in one direction, it will make spacing 18 larger in one side and smaller on another side, and it may lead to leakage between two adjacent floating gates of the smaller CG-to-SL spacing. A sufficient CG-to-SL spacing 18 has to be kept to avoid this leakage from happening. This spacing is difficult to reduce because of miss-alignment issues between the control gate lines 14 and the source line 16. In addition, the width of source line 16 depends on neck space 24, which may vary depending on definition of lithography and the pattern of sophisticated diffusion (active) OPC (optical proximity correction), which often is needed to better define the corner regions 20 of the isolation regions 10, and thus the SL neck area 22 and SL neck space 24, in a controlled way as critical dimensions shrink.
There is a need to form the source regions in a manner that better facilitates scaling down the size of the memory cell array.